LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 25

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont’d)
NOTES:
BOLD ITALIC = Enhanced Operating Mode.
1. t
2. t
3. EF may be used to determine when the first data word D
rising RCLK edge for EF to change predictably during the current
clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than t
that EF will change state until the next following RCLK edge.
edge and a rising RCLK edge to assure a correct readout of the first data
word D
If t
one more clock cycle delay at 2 t
timing restrictions apply only when the FIFO has been empty (EF = LOW).
D
SKEW2
FRL
0
FRL
always is available on the next cycle after EF has gone HIGH.
(First-Read Latency) is the minimum time between a rising WCLK
Q
D
is not met, D
WCLK
0
0
is the minimum time between a rising WCLK edge and a
0
RCLK
WEN
- D
- Q
in response to the next RCLK edge. Thus, t
REN
EF
OE
EF
17
17
2
0
LOW
may be available either at t
t
ENS
t
DS
DATA WRITE 1
t
ENH
DATA IN OUTPUT REGISTER
t
SKEW2
CLK
SKEW2
+ t
(1)
, then it is not guaranteed
SKEW2
t
FRL
t
REF
(2)
. The First-Read Latency
Figure 11. Empty-Flag Timing
CLK
+ t
FRL
SKEW2
= t
0
may be read.
CLK
, or after
t
REF
+ t
t
A
SKEW2
.
t
ENS
t
DS
t
DATA WRITE 2
REF
t
ENH
t
SKEW2
DATA READ
(1)
t
FRL
t
REF
(2)
t
REF
LH540235/45
540235-10
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