LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 13

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

NOTES:
1. When EMODE is HIGH, and Control Register bits 00-05 are LOW, the FIFO behaves in a manner functionally equivalent to the
2. If EMODE is not asserted (is HIGH), Control Register bits 00-05 remain LOW after a reset operation. However, if EMODE is asserted (is
BOLD ITALIC = Enhanced Operating Mode
2048 x 18/4096 x 18 Synchronous FIFOs
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d)
COMMAND
REGISTER
09, 08, 07
11, 10,
03, 02
IDT72235B/45B FIFO of similar depth and speed grade. Under these conditions, the Control Register is not visible or accessible to the ex-
ternal system which includes the FIFO.
LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits
06-11 are unaffected by EMODE.
BITS
00
01
04
05
06
LLLLL
CODE
HL,
LH
HH
LL
H
H
H
H
H
L
L
L
L
L
EMODE = H
VALUE AFTER RESET
LLLLL
LL
L
L
L
L
L
EMODE = L
LLLLL
HH
H
H
H
H
L
Table 5. Control-Register Format
AFFECTED,
IF ANY
FLAG
PAE
PAF
HF
–
–
–
–
Deassertion of LD does not
reset the programmable-
register write pointer and
read pointer.
Deassertion of LD resets
the programmable-register
write pointer and read
pointer to address Word 0,
the Programmable-Almost-
Empty-Flag-Offset Register.
The change takes effect
after a valid write operation
or a valid read operation,
respectively, to the memory
array.
Set by RCLK, reset by
Set and reset by RCLK.
Set by WCLK, reset by
Set and reset by RCLK.
Set and reset by WCLK.
Set by WCLK, reset by
Set and reset by WCLK.
OE has no effect on an
internal read operation,
apart from disabling the
outputs.
Deassertion of OE inhibits
a read operation; whenever
the data outputs Q
are in the high-Z state, the
read pointer does not
advance.
Reserved.
Reserved.
WCLK.
RCLK.
RCLK.
DESCRIPTION
0
– Q
17
IDT-compatible addressing
of programmable registers.
Non-ambiguous
addressing of
programmable registers.
Asynchronous flag
clocking.
Synchronous flag clocking.
Asynchronous flag
clocking.
Synchronous flag clocking
at output port.
Synchronous flag clocking
at input port.
Asynchronous flag
clocking.
Synchronous flag clocking.
Allows the read-address
pointer to advance even
when Q
driving the output bus.
Inhibits the read-address
pointer from advancing
when Q
driving the output bus;
thus, guards against data
loss.
Future use to control depth
cascading and interlocked
paralleling.
Reserved.
0
0
– Q
– Q
NOTES
17
17
LH540235/45
are not
are not
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