LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 11

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

BOLD ITALIC = Enhanced Operating Mode
2048 x 18/4096 x 18 Synchronous FIFOs
KEY:
H = Logic ‘HIGH’; L = Logic ‘LOW’; X = ‘Don’t-care’ (logic ‘HIGH,’ logic ‘LOW,’ or any transition);
NOTES:
1. The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the se-
2. The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is
3. After normal FIFO operation has begun, writing new contents into either of the offset registers should only be done when the FIFO is empty.
4. WEN
= A ‘LOW’-to-‘HIGH’ transition; – = Any condition EXCEPT a ‘LOW’-to-‘HIGH’ transition.
LD
H
H
H
H
H
H
H
H
L
L
L
L
L
L
lection for writing; the other state machine controls the selection for reading. These two state machines operate independently of each other.
Both state machines are reset to point to Word 0 by a reset operation. In the Enhanced Operating Mode, if Control Register bit 00 is set,
both state machines are also reset to point to Word 0 by deassertion of LD after LD has been asserted (that is, by a rising edge of
LD), followed by a valid memory array write cycle for the writing-control state machine and/or by a valid memory array read cycle
for the reading-control state machine.
always:
The order of the three programmable registers which are accessible in Enhanced Operating Mode, as selected by either state
machine, is always:
Note that, in IDT-Compatible Operating Mode, Word 2 is not accessed; Word 0 and Word 1 alternate.
input and of Control Register bit 05.
Word 0: Almost-Empty Offset Register
Word 1: Almost-Full Offset Register
Word 0: Almost-Empty Offset Register
Word 0: Almost-Empty Offset Register
Word 1: Almost-Full Offset Register
Word 2: Control Register
Word 0: Almost-Empty Offset Register
2
, REN
WEN
(repeats indefinitely)
(repeats indefinitely)
X
H
H
H
X
H
X
X
H
L
L
L
L
L
...
...
2
3,4
, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control
REN
X
H
H
H
X
X
X
H
H
L
L
L
L
L
3,4
WCLK
X
X
X
X
X
X
X
–
–
–
Table 3. Selection of Read and Write Operations
RCLK
X
X
X
X
X
X
X
–
–
–
No operation.
Illegal combination, which will cause errors.
Write to a programmable register.
Hold present value of programmable-register write counter, and do not write.
Read from a programmable register.
Hold present value of programmable-register read counter, and do not read.
Normal FIFO write operation.
Normal FIFO read operation.
No write operation.
No write operation.
No read operation.
No read operation.
No operation.
No operation.
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ACTION
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LH540235/45
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