LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 20

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

LH540235/45
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
that is, whenever subtracting the value of the FIFO’s
internal write pointer from the value of its internal read
pointer yields a difference which is less than q + 1, where
‘q’ is the value of the Programmable-Almost-Empty-Flag
Offset. The subtraction is performed using modular arith-
metic, modulo the total nominal number of 18-bit words
in the FIFO’s physical memory, which is 2048 for the
LH540235 or 4096 for the LH540245 respectively.
operation is 127
which does not exceed this total nominal number of words
for the device, as explained in the description of Load
(LD).
no write operations have been performed since the com-
pletion of the reset operation, then PAE is LOW (see Table
4).
the FIFO is from one-eighth full to completely empty.
from HIGH to LOW only after a LOW-to-HIGH transition
of the Read Clock RCLK, and from LOW to HIGH only
after a LOW-to-HIGH transition of the Write Clock WCLK.
Thus, in this operating mode, PAE behaves as an ‘asyn-
chronous flag.’
hand, PAE gets updated only after a LOW-to-HIGH
transition of the Read Clock RCLK, and thus behaves
as a ‘synchronous flag,’ whenever Control Register
bit 01 is HIGH (see Table 5).
EMPTY FLAG (EF)
That is, whenever the FIFO’s internal read pointer has
completely caught up with its internal write pointer; so
that, if another word were to be read out, it would have to
come from the physical memory location which is now in
position to be written into by the next requested write
operation. Read operations are inhibited whenever EF is
LOW, regardless of the assertion or deassertion of Read
Enable (REN).
no write operations have been performed since the
completion of the reset operation, then EF is LOW. (See
Table 4.)
Read Clock RCLK.
READ EXPANSION OUT/ EMPTY FLAG 2 (RXO/ EF
operation, it has no function. In IDT-compatible ‘cas-
caded’ operation, it behaves as a Read Expansion Output
BOLD ITALIC = Enhanced Operating Mode
20
PAE goes LOW whenever the FIFO is ‘almost empty’;
The default value of q after the completion of a reset
If the FIFO has been reset by asserting RS (LOW), and
If q is still at its default value, PAE is LOW whenever
In the IDT-Compatible Operating Mode, PAE changes
In the Enhanced Operating Mode, on the other
EF goes LOW whenever the FIFO is completely empty.
If the FIFO has been reset by asserting RS (LOW), and
EF gets updated after a LOW-to-HIGH transition of the
RXO/ EF
2
is a dual-purpose signal. In ‘standalone’
10
. However, q may be set to any value
2
)
(RXO) signal to coordinate writing operations with the
next FIFO in the cascade. Under these same conditions,
also, the dual purpose RXI/ REN
behave as Read Expansion Input (RXI) and Write Expan-
sion Input (WXI) signals respectively.
operating in IDT-compatible ‘cascaded’ mode as a deeper
‘effective FIFO,’ the dual-purpose RXI/ REN
WXI/ WEN
and Write Expansion Input (WXI) signals respectively. An
IDT-style cascade of these FIFO devices has a ‘daisy-
chain’ ring configuration; the Read Expansion Input (RXI)
of each FIFO is connected to RXO (RXO/ EF
as RXO) of the previous FIFO in the ring, with RXI of the
‘first-load’ or ‘master’ FIFO being connected to RXO of
the last FIFO so as to complete the ring. Similar connec-
tions are made for each FIFO in the ring, parallel to these
RXO-to-RXI connections, for Write Expansion Input
(WXI) and Write Expansion Output (WXO).
FIFO operating in IDT-style cascaded mode, a LOW-go-
ing pulse is emitted by that FIFO on its RXO output;
otherwise, RXO remains constantly HIGH. This LOW-go-
ing RXO pulse serves as a ‘read token’ in the token-pass-
ing FIFO-cascading scheme; it is passed on to the next
FIFO in the ring via its RXI input. When this next FIFO
receives the read token, it is activated for reading at the
next valid RCLK.
vated for reading at the next valid RCLK. Also, its data
outputs go into high-Z state, regardless of the assertion
or deassertion of its Output Enable (OE) control input,
until it again receives the token. Simultaneously, the next
FIFO in the ring is activated for reading.
or ‘master’ FIFO in the ring, and to any and all ‘slave’
FIFOs in the ring. However, RXO has no necessary
function for a FIFO which is operating in ‘standalone’
mode. Consequently, in that mode, RXO is never as-
serted, and remains constantly HIGH. A FIFO is initialized
into ‘standalone’ mode, into ‘cascaded master’ mode, or
into ‘cascaded slave’ mode according to the state of its
WXI/ WEN
a reset operation. It also may be forced into inter-
locked-paralleled mode by EMODE (see Table 1, Ta-
ble 2, and Table 5).
haves as a second Empty Flag EF
duplicate of the main Empty Flag EF, except that it is
delayed with respect to EF By one full cycle of the
Read Clock RCLK.
When two or more LH540235 or LH540245 FIFOs are
After a FIFO emits an RXO pulse, the FIFO is deacti-
The foregoing description applies both to the ‘first-load’
In the Enhanced Operating Mode, RXO/EF
When the last physical location has been read in a
2
2
, RXI/ REN
inputs behave as Read Expansion Input (RXI)
2048 x 18/4096 x 18 Synchronous FIFOs
2
, and FL/ RT control inputs during
2
and WXI/ WEN
2
. EF
2
is an exact
2
, behaving
2
2
inputs
2
and
be-