LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 18

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

LH540235/45
WRITE EXPANSION INPUT/ WRITE ENABLE 2
(WXI/ WEN
input signals which select the grouping mode in which the
FIFO operates after being reset; the other three of these
input signals are FL/ RT , RXI/ REN
are four possible grouping modes: standalone, inter-
locked paralleled , cascaded ‘master’ or ‘first-load,’ and
cascaded ‘slave.’ The designations ‘master’ and ‘slave’
pertain to IDT-compatible depth cascading. Tables 1 and
2 show the signal encodings which select each grouping
mode.
both must be grounded so that the FIFO comes up in the
standalone grouping mode after a reset operation. In
interlocked-paralleled operation, WXI/WEN
FF of the other paralleled FIFO, and RXI/REN
to EF of that same other FIFO. This interconnection
scheme ensures that both FIFOs will operate
together, and remain coordinated, regardless of tim-
ing skews.
WXO (Write Expansion Output; actually WXO/HF) output
of the previous FIFO in the cascade. RXI/ REN
connected to the RXO (Read Expansion Output; actually
RXO/ EF
forces WXO/HF and RXO/ EF
consequently, all FIFOs with their WXI/ WEN
RXI/ REN
two cascaded grouping modes, according to whether
their FL/ RT inputs are grounded or tied HIGH (see Tables
1 and 2).
READ EXPANSION INPUT/ READ ENABLE 2
(RXI/ REN
input signals which select the grouping mode in which the
FIFO operates after being reset; the other three of these
input signals are FL/ RT , WXI/ WEN
are four possible grouping modes: standalone, inter-
locked-paralleled , cascaded ‘master’ or ‘first-load,’ and
cascaded ‘slave.’ The designations ‘master’ and ‘slave’
pertain to IDT-compatible depth cascading. Tables 1 and
2 show the signal encodings which select each grouping
mode.
both must be grounded, so that the FIFO comes up in the
standalone grouping mode after a reset operation. In
interlocked-paralleled operation, WXI/WEN
FF of the other paralleled FIFO, and RXI/REN
to EF of that same other FIFO. This interconnection
scheme ensures that both FIFOs will operate to-
gether, and remain coordinated, regardless of timing
skews.
BOLD ITALIC = Enhanced Operating Mode
18
WXI /WEN
In standalone operation, WXI/ WEN
In cascaded operation, WXI/ WEN
RXI /REN
In standalone operation, WXI/ WEN
2
2
) output of that previous FIFO. A reset operation
2
inputs thus connected come up in one of the
2
)
2
)
2
is a dual-purpose signal. It is one of four
is a dual-purpose signal. It is one of four
2
HIGH for each FIFO;
2
2
, and EMODE . There
, and EMODE . There
2
is connected to the
2
2
and RXI/ REN
and RXI/ REN
2
2
2
is likewise
is tied to
is tied to
2
2
is tied
2
is tied
and
2
2
RXO (Read Expansion Output; actually RXO/ EF
previous FIFO in the cascade. WXI/ WEN
connected to WXO (Write Expansion Output; actually
WXO/HF) output of that previous FIFO. A reset operation
forces RXO/ EF
consequently, all FIFOs with their RXI/ REN
WXI/ WEN
two IDT-compatible cascaded grouping modes, accord-
ing to whether their FL/ RT inputs are grounded or tied
HIGH (see again Tables 1 and 2).
Data Outputs
DATA OUT (Q
Register codes are output from the FIFO as 18-bit words
on Q
and Control-Register words are zero-filled.
Control/Status Outputs
FULL FLAG (FF)
That is, whenever the FIFO’s internal write pointer has
completely caught up with its internal read pointer; so that,
if another word were to be written, it would have to
overwrite the unread word which is now in position for
reading out by the next requested read operation. Under
these conditions, the FIFO is filled to its nominal capacity,
which is 2048 18-bit words for the LH540235 or 4096
18-bit words for the LH540245 respectively. Write opera-
tions are inhibited whenever FF is LOW, regardless of the
assertion or deassertion of Write Enable (WEN).
initially is HIGH. But, whenever no read operations have
been performed since the completion of the reset opera-
tion, FF goes LOW after 2048 write operations for the
LH540235, or after 4096 write operations for the
LH540245 (see Table 4).
Write Clock (WCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
is, whenever subtracting the value of the FIFO’s internal
read pointer from the value of its internal write pointer
yields a difference which is less than the value of the
Programmable-Almost-Full-Flag Offset ‘p.’ The subtrac-
tion is performed using modular arithmetic, modulo the
total nominal number of 18-bit words in the FIFO’s physi-
cal memory, which is 2048 for the LH540235 or 4096 for
the LH540245 respectively.
In cascaded operation, RXI/ REN
Data, programmable-flag-offset values, and Control-
FF goes LOW whenever the FIFO is completely full.
If the FIFO has been reset by asserting RS (LOW), FF
FF gets updated after a LOW-to-HIGH transition of the
PAF goes LOW whenever the FIFO is ‘almost’ full; that
0
– Q
2
17
inputs thus connected come up in one of the
2048 x 18/4096 x 18 Synchronous FIFOs
. Unused bit positions in offset-value words
0
2
– Q
and WXO/HF HIGH for each FIFO;
17
)
2
is connected to
2
is likewise
2
)) of the
2
and