LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 21
LH540235M-20
Manufacturer Part Number
LH540235M-20
Description
2048 x 18 / 4096 x 18 Synchronous FIFOs
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
1.LH540235M-20.pdf
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2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS
NOTES:
NOTE:
1. t
1. After reset, the outputs will be LOW if OE = LOW, and in a high-impedance state if OE = HIGH.
2. The clocks (RCLK, WCLK) may be free-running during a reset operation.
rising WCLK edge for FF to change predictably during the current
clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than t
that FF will change state until the next following WCLK edge.
SKEW1
is the minimum time between a rising RCLK edge and a
REN, WEN, LD
FF, PAF, HF
D
WCLK
0
RCLK
WEN
- D
REN
EF, PAE
Q
FF
0
17
- Q
RS
17
t
SKEW1
Figure 7. Synchronous Write Operation
SKEW1
(1)
, then it is not guaranteed
t
Figure 6. Reset Timing
CLKH
t
t
t
t
RSF
RSF
RSF
WFF
t
RS
t
CLK
t
RSS
t
CLKL
t
ENS
DATA IN
t
VALID
DS
t
DH
t
ENH
t
RSR
t
WFF
NO OPERATION
OE = LOW
OE = HIGH
1
540235-5
540235-6
LH540235/45
21
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