SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 88
SDA5523
Manufacturer Part Number
SDA5523
Description
SDA55xx TVText Pro
Manufacturer
Micronas Semiconductor
Datasheet
1.SDA5523.pdf
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SDA 55xx
To decide the levels of COR and BLANK for BOX1 two
global parameters are used.
Table 2–65: COR/BLANK polarity of BOX1
2.13.7.5. CLUT
Table 2–66: COR/BLANK polarity setup for hardware CLUT during black clamp phase
88
COR_BOX1
0
0
1
1
See also Section 2.13.5. on page 75-Global Display Word (GDW)
HDWCLUTCOR
0
0
1
1
BLA_BOX1
0
1
0
1
HDWCLUTBLANK
0
1
0
1
Description
Box transparency levels of COR and BLANK for BOX1 are overruled by:
COR = 0; BLANK = 0
Box transparency levels of COR and BLANK coming from CLUT0 inside BOX1 are
overruled by:
COR = 0; BLANK = 1
Box transparency levels of COR and BLANK coming from CLUT0 inside BOX1 are
overruled by:
COR = 1; BLANK = 0
Box transparency levels of COR and BLANK coming from CLUT0 inside BOX1 are
overruled by:
COR = 1; BLANK = 1
Description
Decides the polarity for COR and BLANK output for the hardwired CLUT
entries 0-15 and the polarity of COR and BLANK during black clamp
phase (See also Section 2.12.1. on page 66):
COR = 0
BLANK = 0
Decides the polarity for COR and BLANK output for the hardwired CLUT
entries 0-15 and the polarity of COR and BLANK during black clamp
phase (See also Section 2.12.1. on page 66):
COR = 0
BLANK = 1
Decides the polarity for COR and BLANK output for the hardwired CLUT
entries 0-15 and the polarity of COR and BLANK during black clamp
phase (See also Section 2.12.1. on page 66):
COR = 1
BLANK = 0
Decides the polarity for COR and BLANK output for the hardwired CLUT
entries 0-15 and the polarity of COR and BLANK during black clamp
phase (See also Section 2.12.1. on page 66):
COR = 1
BLANK = 1
Sept. 10, 2004; 6251-556-3DS
DATA SHEET
Micronas
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