SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 44

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.3.16. Interrupt Task Function
The microcontroller records the active priority level(s)
by setting internal flip-flop(s). Each interrupt level has
its own flip-flop. The flip-flop corresponding to the inter-
rupt level being serviced is reset when the microcon-
troller executes a RETI-instruction.
The sequence of events for an interrupt is:
– A source provokes an interrupt by setting its associ-
– The interrupt request is conditioned by bits in the
– The microcontroller acknowledges the interrupt by
– The service program is executed.
– Control is returned to the main program when the
The interrupt request flags IE0, IE1, TF0 and TF1 are
cleared when the microcontroller transfers control to
the first instruction of the interrupt service program.
Table 2–25: Related registers
44
Register Name
PSAVE
PSAVEX
bit addressable
PCON
See Section 3. on page 110 for detailed register description.
ated interrupt request bit to let the microcontroller
know an interrupt condition has occurred.
interrupt enable and interrupt priority registers.
setting one of the four internal ‘priority-level active’
flip-flops and performing a hardware subroutine call.
This call pushes the PC (but not the PSW) onto the
stack and, for some sources, clears the interrupt
request flag.
RETI-instruction is executed. The RETI- instruction
also clears one of the internal ‘priority-level active’
flip-flops.
7
SMOD
6
PDS
5
IDLS
Sept. 10, 2004; 6251-556-3DS
4
CADC
SD
2.3.17. Power Saving Modes
The controller provides four modes in which power
consumption can be significantly reduced.
– Idle mode: The CPU is gated off from the oscillator.
– Power-down mode: Operation of the controller is
– Power-save mode: In this mode display generator,
– Slow-down mode: In this mode the system fre-
All modes are entered by software. Special function
register is used to enter one of these modes.
2.3.18. Power-Save Mode Registers.
The Table 3-25 lists the respective registers which con-
trol or reflect the Power-Save Modes. A description is
given below.
Bit Name
All peripherals except WDT (in watch dog mode) are
still provided with the clock and are able to work.
turned off. This mode is used to save the contents of
internal RAM with a very low standby current.
Slicer_acq_sync, VADC, CADC, ADC_wakeup,
PWM, CRT, WDT, DAC, PLL, and Display (display,
pixel clock and D sync) can be turned off.
quency is reduced by one fourth.
3
WAKUP
GF1
2
SLI_ACQ
Clk_src
GF0
1
DISP
PLL_res
PDE
DATA SHEET
0
PERI
PLLS
IDLE
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