SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 126

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
Table 3–4: SFR register description, continued
126
Name
WDT_high
WDThi[7:0]
CRT_rell
RelL[7:0]
CRT_relh
RelH[7:0]
CRT_capl
CapL[7:0]
CRT_caph
CapH[7:0]
CRT_mincapl
MinL[7:0]
CRT_mincaph
MinH[7:0]
CRT_con0
OV
PR
PLG
REL
RUN
RISE
FALL
SEL
CRT_con1
PR1
First
Start
Sub
hB5
hB5[7:0]
hB7
hB7[7:0]
hB9
hB9[7:0]
hBA
hBA[7:0]
hBB
hBB[7:0]
hBC
hBC[7:0]
hBD
hBD[7:0]
hBE
hBE[7]
hBE[6]
hBE[5]
hBE[4]
hBE[3]
hBE[2]
hBE[1]
hBE[0]
hBF
hBF[2]
hBF[1]
hBF[0]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
0
h00
0
h00
0
h00
0
h00
0
h00
0
h00
0
h00
0
0
0
0
0
0
0
0
h00
0
0
0
Sept. 10, 2004; 6251-556-3DS
0..255
0..255
Range
0..255
0..255
0..255
0..255
0..255
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
CRT
Function
WDT Timer High
Counter value of the watchdog timer; high byte.
CRT Reload Low
CRT reload low byte
CRT Reload High
CRT reload high byte
CRT Capture Low
CRT capture low byte
CRT Capture High
CRT capture high byte
CRT Min Capture Low
CRT min capture low
CRT Min Capture High
CRT min capture high
CRT Control 0
Will be set by hardware, if counter overflow has occurred; must be
cleared by software.
If cleared, 2-bit prescaler; if set, 3-bit prescaler.
If set, Timer polling mode selected, capture function is automatically
disabled, reading capture registers will now show current timer value.
If set, counter will be reloaded simultaneously with capture event.
Run/stop the CRT counter.
Capture (and if REL = ë1í, reload) on rising edge.
Capture (and if REL = ë1í, reload) on falling edge.
If set, P3.3 is selected for capture input, otherwise P3.2.
CRT Control 1
1: Divides input further by 8.
0: Not divided by 8.
1: Indicates first event.
0: Indicates not first event.
1: Controller sets this bit enter the SSU mode and to indicate it is
expecting a new telegram. When an event occurs CAPUTR unit sets
First bit. Upon next event, hardware resets the first bit and interrupt is
generated based on MIN_CAP register.
0: Not SSU mode.
DATA SHEET
Micronas