SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 15

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.2.2.1. Distortion Processing
After A/D conversion the digital CVBS bit stream is
applied to internal circuitry which corrects the input
signal for distortions created in the transmission chan-
nel. In order to apply the right algorithm for the correc-
tion, a signal measurement is done in parallel. This
measurement unit can detect the following distortions.
2.2.2.1.1. Noise
The noise measurement unit incorporates two different
algorithms. Both algorithms use the value between two
equalizing pulses, which corresponds to the black
level. As the system knows the black level, a window is
placed between this two equalizing pulses (located in
line 4).
The first algorithm compares successive the amplitude
samples inside that window. The difference between
these samples is measured and a flag is set as soon
as this difference over several TV lines is greater than
a specified value. This algorithm is able to detect
higher frequency noise (e.g. white noise).
The second algorithm measures the difference
between the black value and the actual sampled value
inside this window. As soon as this difference over sev-
eral TV lines is greater than a specified value a second
flag is set. This algorithm is sensitive against low fre-
quency noise as it is known from co-channel distortion.
Both flags can be used to optimize the response of the
compensation circuits in order to achieve best recep-
tion performance.
2.2.2.1.2. Frequency Attenuation
During signal transmission the CVBS signal can
severely be attenuated. This attenuation normally is
frequency depending. That means that the higher the
frequency the stronger the attenuation. As the clock
run-in (from now on referred to as CRI) for teletext rep-
resents the highest possible frequency (3.5 MHz) it
can be used to measure the attenuation. Only strong
negative attenuation causes problems during data slic-
ing. A flag is needed to notify highly negative attenua-
tion to the SW. If this flag is set a special peaking filter
is switched on in the data-path.
2.2.2.1.3. Group Delay
Quite often the data stream is corrupted because of
group delay distortion introduced by the transmission
channel. The teletext framing code (E4
measurement reference. The delay of the edges inside
this code can be used to measure the group delay dis-
Micronas
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Sept. 10, 2004; 6251-556-3DS
tortion. The measurement is done during every teletext
line and filtered over several lines.
It can be detected whether the signal has positive,
negative or no group delay distortions. Two flags are
set accordingly. By means of these two flags, an all-
pass contained in the compensation circuit is config-
ured to compensate positive or negative group delay.
All of the above mentioned filters can be individually be
disabled, set to forced mode, or automatic mode via
control registers.
2.2.2.2. Data Separation
Parallel to signal analysis and distortion compensation
another filter is calculating the required slicing level.
The slicing level is the mean value of the clock run-in
CRI. As teletext is coded using the NRZ format, the
slicing level can not be calculated outside the CRI tim-
ing window and is therefore frozen after CRI. Using the
found slicing level the data are sliced from the digitized
CVBS signal. The result is a stream of zeros and ones.
In order to find the logical zeros and ones which have
been transmitted, the data clock needs to be recov-
ered. Therefore during the CRI timing window a digital
data PLL (D-PLL) is synchronized to the transitions in
the sliced data stream which represent the original
data clock. The frequency of the D-PLL is also frozen
after the CRI timing window.
Timing information to freeze the slicing level, the D-
PLL and to control other actions are generated by the
timing circuit. It generates also all control signals which
have to be synchronized to the data start.
2.2.3. H/V-Synchronization
Data slicer and acquisition interface require different
control signals which have to be synchronized to the
incoming CVBS (e.g. line number, field sequence or
line start of a TV line). Therefore a slicing level for the
sync pulses is calculated and the sync signal is sliced
from the filtered digital CVBS signal.
Using a digital integrator vertical and horizontal sync
pulses are separated. The horizontal pulses are fed
into a digital H-PLL which has flywheel functionality.
The H-PLL includes a counter which is used to gener-
ate all the necessary horizontal control signals. The
vertical sync pulse is used to synchronize the line
counter, which generates the required vertical control
signals.
The synchronization block includes a watchdog for
supervision of the actual lock condition of the H-PLL.
The watchdog can produce an interrupt (CC_IR) if syn-
chronization has been lost. It could therefore be an
indication for a channel change or missing input signal.
SDA 55xx
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