SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 16

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.2.4. Acquisition Interface
The acquisition interface manages the data transfer
from between slicer and memory. From slicer to mem-
ory first of all a bit synchronization is performed (Fram-
ing Code (FC) check). Following this, the data is serial/
parallel converted. 8 bit wide words will be shifted into
the memory. The data acquisition supports several fea-
tures. The FC check is able to handle four different
framing codes for one field. Two of this framing codes
are programmable and could therefore be changed
from field to field. The acquisition can be switched from
normal mode (line 6 to 23) to full channel mode (line 6
to the end of a field).
In the other direction parameters are loaded from the
memory to the slicer. This parameter down loading
takes place after the vertical sync and after the hori-
zontal sync. These parameters are used for the slicer
configuration.
2.2.4.1. Framing Code Check
There are four Framing Codes FC implemented which
are compared with the FC of the incoming signal.
– The first one is 8-bit wide and is loaded down with
– The second one is 16-bit wide and fixed to the FC of
– The third one is 16-bit wide as well, but can be
– The fourth FC is reserved for WSS. The actual FC
2.2.4.1.1. Framing Code FC1
This FC should be used for all services with 8-bit fram-
ing codes (e.g. for TTX). The actual framing code is
loaded down each field. The check can be done with-
out any bit error tolerance or with a tolerance of one
bit.
2.2.4.1.2. Framing Code FCVPS
This FC is fixed to that of VPS. Only an error-free sig-
nal will enable the reception of the VPS data line.
Note: If VPS should be sliced in field 1 and TTX in field
16
the field parameters.
VPS.
loaded with the field parameters. If the third one is
used, the user can specify not only the FC but also a
“don’t-care” mask.
can be changed line by line.
2, the appropriate line parameters for line 16
have to be changed dynamically from field to
field.
Sept. 10, 2004; 6251-556-3DS
2.2.4.1.3. Framing Code FC3
This 16-bit FC is loaded with the field parameters as
well as a “don’t care” mask. The incoming signal is
compared with both, the framing code and the “don’t
care” mask. Further reception is enabled if all bits
which are not “don’t care” match the incoming data
stream.
2.2.4.1.4. Framing Code FCWSS
This FC is pre-programmed to that of WSS. Only an
error-free signal will enable the reception of the WSS
data line.
2.2.4.1.5. FC Check Select
There is a two bit line parameter called FCSEL. By
means of this parameter the user is able to select
which FC check is used for the actual line. If NORM is
set to WSS the WSS FC check is used independently
of FCSEL.
2.2.4.2. Interrupts
Some events which occur inside the slicer, sync sepa-
ration or acquisition interface should cause an inter-
rupt. They are summarized in register CISR0 and
CISR1. The slicer hardware sets the related interrupt
flag which must be reset by the application software
before the next interrupt can be accepted.
2.2.4.3. VBI Buffer and Memory Organization
The implemented SW has to provide configuration
parameters for the slicer and the acquisition interface.
Both circuits will produce status information for the
CPU.
Some of these parameters and status bits are constant
during the duration of a field. Those parameters are
called field parameters. They are downloaded after the
vertical sync.
Other parameters and status bits may change from
line to line (e.g. data service depending values). Those
parameters are called line parameters. They are down-
loaded after each horizontal sync impulse.
The start address of the VBI buffer can be configured
with a special function register ‘STRVBI’. 9 Bytes are
needed for the field parameter. 47 Bytes should be
reserved for every sliced data line. If 18 lines of data
(in full channel mode 314) have been send to memory
no further data acquisition will take place until the next
vertical pulse appears and the H-PLL is still locked.
DATA SHEET
Micronas