SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 150
SDA5523
Manufacturer Part Number
SDA5523
Description
SDA55xx TVText Pro
Manufacturer
Micronas Semiconductor
Datasheet
1.SDA5523.pdf
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SDA 55xx
150
PMQFP
100-1
19
20
21
22
23
24
25
26
27
28
29
30
PMQFP
64-1
−
−
8
9
10
12
13
14
15
−
16
17
Pin No.
PSDIP
52-1
52-2
−
−
12
13
14
15
16
17
18
−
19
20
PLCC
84-1
−
−
25
26
27
28
29
30
31
−
32
33
Pin Name
OCF
EXTIF
CVBS
VDDA 2.5
VSSA
P2.0
P2.1
P2.2
P2.3
−
HS/SSC
VS
Sept. 10, 2004; 6251-556-3DS
Type
I
I/O
I/O
PS
PS
I/O
I/O
I/O
I/O
−
I/O
I/O
Connection
(If not used)
NC
Short Description
Opcode Fetch. Emulation
control line. A high level
driven by the controller dur-
ing output phase indicates
the beginning of a new
instruction.
This pin must be pulled low
to enable extended mem-
ory interface.
CVBS input for the acquisi-
tion circuit
Supply voltage for analog
components.
Ground for analog compo-
nents
Port 2 is a 4-bit port without
pull-up resistors.
----------
Port 2 has an alternate
function.
See Section on page 155.
Not connected
In slave mode horizontal
sync input or sandcastle
input for display synchroni-
zation.
----------
In master mode HS or VCS
output
Vertical sync input/ouput for
display synchronization.
----------
It also can be used as digital
input P4.7.
See Section on page 155.
----------
Furthermore, this pin can be
selected as an ODD/EVEN
indicator alternatively to
P3.0.
See Section on page 155.
DATA SHEET
Micronas
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