SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 136

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SDA5523

Manufacturer Part Number
SDA5523
Description
SDA55xx TVText Pro
Manufacturer
Micronas Semiconductor
Datasheet
SDA 55xx
Table 3–4: SFR register description, continued
136
Name
VS_OE
O_E_P3_0
O_E_Pol
CSCR1
IntSrc1
IntSrc0
ENARW
A19_P4_4
A18_P4_1
A17_P4_0
Sub
hDD[2]
hDD[1]
hDD[0]
hDE
hDE[7)
hDE[6]
hDE[3]
hDE[2]
hDE[1]
hDE[0]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
h00
h00
h00
h00
h00
h00
h00
h00
h00
Sept. 10, 2004; 6251-556-3DS
Range
Function
0: P4.7 alternate output mode, Odd/Even selected
1: P4.7 alternate output mode, Vertical Sync selected
See Section 2.13. on page 69 register SCR0, for Vertical Sync details
0: Port 3.0 port mode selected
1: Port 3.0 works as a Odd/Even output
0: Odd = 1, Even = 0
1: Odd = 0, Even = 1
Note: Polarity is true for both P3.0 and P4.7,
Central Special Control 1
0: Port 3.3 is the source of the interrupt,
1: SSU is the source of interrupt,(Application Note: Use with SEL 0 0),
0: Port 3.3 is the source of the interrupt,
1: SSU is the source of interrupt,(Application Note: Use with SEL 0 1),
0: Port P4.2 and P4.3 function as port pins
1: Port 4.2 and P4.3 function as RD and WR signal outputs.
0: Pin functions as address line
1: Pin function as port
0: Pin functions as address line
1: Pin function as port
0: Pin functions as address line
1: Pin function as port
DATA SHEET
Micronas

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