SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 133

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
Table 3–4: SFR register description, continued
Micronas
Name
HCR0
BHCR[7:0]
BVCR
BVCR[9:8]
BVCR0
BVCR[7:0]
EVCR1
EVCR[9:8]
EVCR0
EVCR[7:0]
VLR1
Odd_Ev
Sub
hE9
hE9[7:0]
hEA
hEA[1:0]
hEB
hEB[7:0]
hEC
hEC[1:0]
hED
hED[7:0]
hEE
hEE[6]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
0
h00
0
h00
0
h00
0
h04
4
h02
0
Sept. 10, 2004; 6251-556-3DS
Range
0..255
0..3
0..255
0..3
0..255
0..1
Function
DSync H Clamp Begin
Beginning of Horizontal Clamp Phase (master and slave mode)
This register defines the delay of the horizontal clamp phase from the
positive edge of the horizontal sync impulse (normal polarity is
assumed). The beginning of clamp phase can be calculated by the
following formula:
tH_clmp_b = 480 ns * BHCR
If EHCR is smaller than BHCR the clamp phase will appear during
Hsync.
DSync V Clamp Begin 1
Beginning of Vertical Clamp Phase (master and slave mode)
This register defines the beginning of the vertical clamp phase from
the positive edge of the vertical sync impulse (at normal polarity) in
count of lines.
If EVCR is smaller than BVCR than the clamp phase will appear
during Vsync.
DSync V Clamp Begin 0
Beginning of Vertical Clamp Phase (master and slave mode)
This register defines the beginning of the vertical clamp phase from
the positive edge of the vertical sync impulse (at normal polarity) in
count of lines.
If EVCR is smaller than BVCR than the clamp phase will appear
during Vsync.
DSync V Clamp End 1
End of Vertical Clamp Phase (master and slave mode)
This register defines the end of the vertical clamp phase from the
positive edge of the vertical sync impulse (at normal polarity) in count
of lines.
If EVCR is set to a value smaller than BVCR than the vertical blanking
phase will last over the vertical blanking interval.
If EVCR is smaller than BVCR than the clamp phase will appear
during Vsync.
DSync V Clamp End 0
End of Vertical Clamp Phase (master and slave mode)
This register defines the end of the vertical clamp phase from the
positive edge of the vertical sync impulse (at normal polarity) in count
of lines.
If EVCR is set to a value smaller than BVCR than the vertical blanking
phase will last over the vertical blanking interval.
If EVCR is smaller than BVCR than the clamp phase will appear
during Vsync.
DSync Vertical Line 1
ODD/EVEN detection (slave mode only)
Used as a interface from the hardware odd/even field detection to
software.
Set to 1 for odd fields and to 0 for even fields.
SDA 55xx
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