HD6433935 Hitachi, HD6433935 Datasheet - Page 393

• Manufacturer Part Number: HD6433935
• Description: 8-Bit MICROCONTROLLER
• Manufacturer: Hitachi

Table 12-32 Alphanumeric Message without fragmentation
PACKET
1st
2nd
3rd
4th
Note:
packets decrement the count for the first fragment and the last fragment. This dec-rements the
all frame counter to zero, if no other fragmented messages, temporary addresses are pending
and the FAF bit is clear in the All Frame Mode Register, the FLEX decoder returns to normal
operation.
The above process must be repeated for each occurrence of a fragmented message. The host
must keep track of the number of fragmented messages being decoded and insure the all frame
mode counter decrements after each fragment or after each fragmented message.
*
Host Initiated Packet. The FLEX decoder returns a packet according to 12.4, Decoder-
to-Host Packet Descriptions.
PACKET TYPE
ADDRESS 1
VECTOR 1
MESSAGE
Variable*
PHASE
A
A
A
All Frame
Counter
0
1
1
0
COMMENT
Address 1 is received
Vector = Alphanumeric Type
Message Word received “C” bit = 0, No
more fragments are expected.
Host writes All Frame Mode Packet to the
FLEX decoder with the “DAF” bit = 1
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