HD6433935 Hitachi, HD6433935 Datasheet - Page 353
HD6433935
Manufacturer Part Number
HD6433935
Description
8-Bit MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6433935.pdf
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12.3.2
The Configuration Packet defines a number of different configuration options for the FLEX
decoder. Proper operation is not guaranteed if these settings are changed when decoding is enabled
(i.e. the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1.
Table 12-4 Configuration Packet Bit Assignments
Byte 3
Byte 2
Byte 1
Byte 0
DFC: Disable Fractional Clock. When this bit is set and IDE is set, the CLKOUT signal will
generate a 40 kHz signal (ø
CLKOUT signal will generate 38.4 kHz signal (ø
below). This bit has no effect when IDE is cleared. (value after reset=0)
IDE: Internal Demodulator Enable. When this bit is set, the internal demodulator is enabled and
the clock frequency at ø
demodulator is disabled and the clock frequency at ø
reset=0)
OFD: Oscillator Frequency Difference. These bits describe the maximum difference in the
frequency of the 76.8 kHz oscillator crystal with respect to the frequency of the transmitter. These
limits should be the worst case difference in frequency due to all conditions including but not
limited to aging, temperature, and manufacturing tolerance. Using a smaller frequency difference
in this packet will result in lower power consumption due to higher receiver battery save ratios.
Note that this value is not the absolute error of the oscillator frequency provided to the FLEX
decoder. The absolute error of the clock used by the FLEX transmitter must be taken into account.
(e.g. If the transmitter tolerance is +/- 25 ppm and the oscillator tolerance is +/-140 ppm, the
oscillator frequency difference is +/- 165 ppm and OFD should be set to 0.)(value after reset = 0)
CLKOUT
w/ DFC=0
CLKOUT
w/ DFC=1
Bit 7
0
0
0
SME
Configuration Packet
ø
DEC
Bit 6
0
DFC
0
MOT
DEC
DEC
is expected to be 160 kHz. When this bit is cleared, the internal
divided by 4). When this bit is cleared and IDE is set, the
Bit 5
0
0
0
COD
Bit 4
0
0
0
MTE
DEC
DEC
fractionally divided by 25/6 see diagram
Bit 3
0
0
0
LBP
is expected to be 76.8 kHz. (value after
Bit 2
0
IDE
PCE
ICO
Bit 1
0
OFD
SP
0
1
1
Bit 0
1
OFD
SP
0
0
0
341
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