HD6433935 Hitachi, HD6433935 Datasheet - Page 392
HD6433935
Manufacturer Part Number
HD6433935
Description
8-Bit MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6433935.pdf
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Additional fragments can be expected when the “continue bit” in the 1st Message Word is set.
This causes the pager to examine every following frame for an additional fragment until the last
fragment with the continue bit reset is found. The only requirement relating to the placement in
time of the remaining fragments is that no more than 32 frames (1 minute) or 128 frames (4
minutes) as indicated by the service provider may pass between fragment receptions.
Each fragment contains a check sum character to detect errors in the fragment, a fragment number
0, 1, or 2 to detect missing fragments, a message number to identify which message the fragment
is a part, and the continue bit which either indicates that more fragments are in queue or that the
last fragment has been received.
The following describes the sequence of events between the Host and the FLEX decoder required
to handle a fragmented message:
380
V
0 0 0
1 0 1
1 1 0
2
The host will receive a vector indicating one of the following types:
The FLEX decoder will increment the all frame mode counter inside the FLEX decoder and
begin to decode all of the following frames.
The host will receive the Message Packet(s) contained within that frame followed by a Status
Packet. The host must decide based on the Message Packet to return to normal decoding
operation. If the message is indicated as fragmented by the Message Continued Flag “C” being
set in the Message Packet then the host does not decrement the all frame mode counter at this
time. The host decrements the counter if the Message Continued Flag “C” is clear by writing
the All Frame Mode Packet to the FLEX decoder with the “DAF” bit = 1. If no other
fragments, temporary addresses are pending and the FAF bit is clear in the All Frame Mode
Register, then the FLEX decoder returns to normal operation.
The FLEX decoder continues to decode all of the frames and passes any address infor-mation,
vector information and message information to the host followed by a status packet indicating
the end of the frame. If the message is indicated as fragmented by the Message Continued Flag
“C” in the Message Packet then the host remains in the receive mode expecting more
information from the FLEX decoder.
After the host receives the second and subsequent fragment with the Message Continued Flag
“C” = 1, it should decrement the all frame mode counter by sending an All Frame Mode Packet
to the FLEX decoder with the “DAF” bit = 1. Alternatively, the host may choose to decrement
the counter at the end of the entire message by decrementing the counter once for each
fragment received.
When the host receives a Message Packet with the Message Continued Flag “C” = 0, it will
send two All Frame Mode Packets to the FLEX decoder with the “DAF” bit = 1. The two
V
1
V
0
Type
Secure
Alphanumeric
Hex / Binary
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