HD6433935 Hitachi, HD6433935 Datasheet - Page 128
HD6433935
Manufacturer Part Number
HD6433935
Description
8-Bit MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6433935.pdf
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4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) 8t
Notation:
t
t
t
t
5.8.3
1. Direct transition from active (high-speed) mode to subactive mode
2. Direct transition from active (medium-speed) mode to subactive mode
3. Direct transition from subactive mode to active (high-speed) mode
4. Direct transition from subactive mode to active (medium-speed) mode
116
osc
w
cyc
subcyc
:
:
:
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
:
Notes on External Input Signal Changes before/after Direct Transition
øw/8 or ø8 is selected as the CPU operating clock, and wait time = 8192 states)
OSC clock cycle time
Watch clock cycle time
System clock (ø) cycle time
Subclock (ø
SUB
processing states) }
to STS0) + (number of interrupt exception handling execution states) }
(t
) cycle time
cyc
after transition)
w
(t
+ (8192 + 14) 16t
subcyc
before transition) + { (wait time set in STS2
osc
= 24t
w
+ 131296t
........................ (4)
osc
(when
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