ATMEGA163 ATMEL [ATMEL Corporation], ATMEGA163 Datasheet - Page 65

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ATMEGA163

Manufacturer Part Number
ATMEGA163
Description
8-bit Microcontroller with 16K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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Serial Peripheral
Interface – SPI
1142E–AVR–02/03
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega163 and peripheral devices or between several AVR devices. The
ATmega163 SPI includes the following features:
Figure 41. SPI Block Diagram
The interconnection between Master and Slave CPUs with SPI is shown in Figure 42.
The PB7(SCK) pin is the clock output in the Master mode and the clock input in the
Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock
generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)
pin of the Slave CPU. After shifting one byte, the SPI Clock Generator stops, setting the
end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to
select an individual Slave SPI device. The two Shift Registers in the Master and the
Slave can be considered as one distributed 16-bit circular Shift Register. This is shown
in Figure 42. When data is shifted from the Master to the Slave, data is also shifted in
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
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DIVIDER
ATmega163(L)
65

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