ATMEGA163 ATMEL [ATMEL Corporation], ATMEGA163 Datasheet - Page 36

• Manufacturer Part Number: ATMEGA163
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Power-down Mode
Power-save Mode
36
ATmega163(L)
When the SM1/SM0 bits are 10, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external inter-
rupts, the Two-wire Serial Interface address match, and the Watchdog continue
operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a
Two-wire Serial Interface address match interrupt, or an external level interrupt can
wake up the MCU.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator
clock, and if the input has the required level during this time, the MCU will wake up. The
period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25 C. The frequency of
the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics
section.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as seen in Table 5 on page 25.
When the SM1/SM0 bits are 11, the SLEEP instruction forces the MCU into the Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-
f lo w o r O u tp u t C o m p a r e e v e n t fr o m Ti me r /C o u n te r2 i f t h e c o r r e s p o n d i n g
Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable
bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recom-
mended instead of Power-save mode because the contents of the registers in the
asynchronous timer should be considered undefined after wake-up in Power-save mode
if AS2 is 0.
1142E–AVR–02/03