ATMEGA163 ATMEL [ATMEL Corporation], ATMEGA163 Datasheet - Page 54

• Manufacturer Part Number: ATMEGA163
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Timer/Counter2 Output
Compare Register – OCR2
Timer/Counter2 in PWM Mode
PWM Modes (Up/Down and
Overflow)
54
ATmega163(L)
The Output Compare Register is an 8-bit read/write register.
The Timer/Counter Output Compare Register contains the data to be continuously com-
pared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A
software write to the Timer/Counter2 Register blocks compare matches in the next
Timer/Counter2 clock cycle. This prevents immediate interrupts when initializing the
Timer/Counter2.
A Compare Match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it
reaches $FF or it acts as an up/down counter.
If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register
– OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on
the PD7(OC2) pin.
If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register
– OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed
of the up/down counting mode.
The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Con-
trol Register – TCCR2.
If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down
counter, counting up from $00 to $FF, where it turns and counts down again to zero
before the cycle is repeated. When the counter value matches the contents of the Out-
put Compare Register, the PD7(OC2) pin is set or cleared according to the settings of
the COM21/COM20 bits in the Timer/Counter Control Register TCCR2.
If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start count-
ing from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to
the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value
matches the contents of the Output Compare Register. Refer to Table 21 for details.
Bit
$23 ($43)
Read/Write
Initial Value
MSB
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
LSB
0
0
1142E–AVR–02/03
OCR2