ATMEGA163 ATMEL [ATMEL Corporation], ATMEGA163 Datasheet - Page 48

• Manufacturer Part Number: ATMEGA163
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Timer/Counter1 Input Capture
Register – ICR1H and ICR1L
Timer/Counter1 in PWM Mode
48
ATmega163(L)
The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program
and also interrupt routines perform access to registers using TEMP, interrupts must be
disabled during access from the main program and interrupt routines.
The Input Capture Register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting – ICES1) of
the signal at the Input Capture Pin – ICP – is detected, the current value of the
Timer/Counter1 Register – TCNT1 – is transferred to the Input Capture Register – ICR1.
At the same time, the Input Capture Flag – ICF1 – is set (one).
Since the Input Capture Register – ICR1 – is a 16-bit register, a temporary register
TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously.
When the CPU reads the Low Byte ICR1L, the data is sent to the CPU and the data of
the High Byte ICR1H is placed in the TEMP Register. When the CPU reads the data in
the High Byte ICR1H, the CPU receives the data in the TEMP Register. Consequently,
the Low Byte ICR1L must be accessed first for a full 16-bit register read operation.
The TEMP Register is also used when accessing TCNT1, OCR1A, and OCR1B. If the
main program and also interrupt routines accesses registers using TEMP, interrupts
must be disabled during access from the main program and interrupt routines.
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A
– OCR1A and the Output Compare Register1B – OCR1B, form a dual 8,- 9-, or 10-bit,
free-running, glitch-free, and phase correct PWM with outputs on the PD5 (OC1A) and
PD4(OC1B) pins. In this mode, the Timer/Counter1 acts as an up/down counter, count-
ing up from $0000 to TOP (see Table 16), where it turns and counts down again to zero
before the cycle is repeated. When the counter value matches the contents of the 8, 9,
or 10 least significant bits (depending on resolution) of OCR1A or OCR1B, the
PD5(OC1A)/PD4(OC1B) pins are set or cleared according to the settings of the
COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register
TCCR1A. Refer to Table 12 on page 44 for details.
Alternatively, the Timer/Counter1 can be configured to a PWM that operates at twice the
speed as in the mode described above. Then the Timer/Counter1 and the Output Com-
pare Register1A – OCR1A and the Output Compare Register1B – OCR1B, form a dual
8-, 9-, or 10-bit, free-running and glitch-free PWM with outputs on the PD5(OC1A) and
PD4(OC1B) pins.
Bit
$27 ($47)
$26 ($46)
Read/Write
Initial Value
MSB
15
R
R
7
0
0
14
R
R
6
0
0
13
R
R
5
0
0
12
R
R
4
0
0
11
R
R
3
0
0
10
2
R
R
0
0
R
R
9
1
0
0
LSB
R
R
8
0
0
0
1142E–AVR–02/03
ICR1H
ICR1L