ATMEGA163 ATMEL [ATMEL Corporation], ATMEGA163 Datasheet - Page 180

• Manufacturer Part Number: ATMEGA163
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Erratas
ATmega163(L) Errata
Rev. F
180
ATmega163(L)
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6. Increased Interrupt Latency
5. Interrupts Abort TWI Power-down
4. TWI Master Does not Accept Spikes on Bus Lines
3. TWCR Write Operation Ignored
Increased Interrupt Latency
Interrupts Abort TWI Power-down
TWI Master Does not Accept Spikes on Bus Lines
TWCR Write Operations Ignored
PWM not Phase Correct
TWI is Speed Limited in Slave Mode
In this device, some instructions are not interruptable, and will cause the interrupt
latency to increase. The only practical problem concerns a loop followed by a two-
word instruction while waiting for an interrupt. The loop may consist of a branch
instruction or an absolute or relative jump back to itself like this:
loop: rjmp loop
<Two-word instruction>
In this case, a dead-lock situation arises.
Problem Fix/Workaround
In assembly, insert a nop instruction immediately after a loop to itself. The problem
will normally be detected during development. In C, the only construct that will give
this problem is an empty “for” loop; “for(;;)”. Use “while(1)” or “do{} while (1)” to avoid
the problem.
TWI Power-down operation may be aborted by other interrupts. If an interrupt (e.g.,
INT0) occurs during TWI Power-down address watch and wakes the CPU up, the
TWI aborts operation and returns to its idle state.
Problem Fix/Workaround
Ensure that the TWI Address Match is the only enabled interrupt when entering
Power-down.
When the part operates as Master, and the bus is idle (SDA = 1; SCL = 1), generat-
ing a short spike on SDA (SDA = 0 for a short interval), no interrupt is generated,
and the status code is still $F8 (idle). But when the software initiates a new start
condition and clears TWINT, nothing happens on SDA or SCL, and TWINT is never
set again.
Problem Fix/Workaround
Either of the following:
1. Ensure that no spikes occur on SDA or SCL lines.
2. Receiving a valid START condition followed by a STOP condition provokes a
3. In a Single Master systems, the user should write the TWSTO bit immedi-
Repeated write to TWCR must be delayed. If a write operation to TWCR is immedi-
ately followed by another write operation to TWCR, the first write operation may be
ignored.
bus error reported as a TWI interrupt with status code $00.
ately before writing the TWSTA bit.
1142E–AVR–02/03