ATMEGA163 ATMEL [ATMEL Corporation], ATMEGA163 Datasheet - Page 111

• Manufacturer Part Number: ATMEGA163
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

The ADC Control and Status
Register – ADCSR
1142E–AVR–02/03
Table 41. Input Channel Selections (Continued)
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress, will terminate this
conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, a logical “1” must be written to this bit to start each conver-
sion. In Free Running mode, a logical “1” must be written to this bit to start the first
conversion. The first time ADSC has been written after the ADC has been enabled, or if
ADSC is written at the same time as the ADC is enabled, an extended conversion will
precede the initiated conversion. This extended conversion performs initialization of the
ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. When a extended conversion precedes a real conversion,
ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no
effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is set (one) the ADC operates in Free Running mode. In this mode, the
ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will
terminate Free Running mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the Data Registers are
updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-
bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond-
ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the
flag. Beware that if doing a Read-Modify-Write on ADCSR, a pending interrupt can be
disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete Interrupt is activated.
Bit
$06 ($26)
Read/Write
Initial Value
MUX4..0
01000..11101
11110
11111
ADEN
R/W
7
0
ADSC
R/W
6
0
ADFR
R/W
5
0
Single-ended Input
Reserved
1.22V (V
0V (AGND)
ADIF
R/W
4
0
BG
ADIE
R/W
)
3
0
ADPS2
R/W
2
0
ATmega163(L)
ADPS1
R/W
1
0
ADPS0
R/W
0
0
ADCSR
111