HYB18M512160BF-7.5 QIMONDA [Qimonda AG], HYB18M512160BF-7.5 Datasheet - Page 7

• Manufacturer Part Number: HYB18M512160BF-7.5
• Description: DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM RoHS compliant
• Manufacturer: QIMONDA [Qimonda AG]

2
The 512-Mbit DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912
bits. It is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR Mobile-RAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command description and device operation.
2.1
2.1.1
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition
includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode
Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the
stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
MR
Mode Register Definition
Field
CL
BT
BL
Internet Data Sheet
BA1
0
Bits
[6:4]
3
[2:0]
BA0
0
Functional Description
Register Definition
Mode Register
Type Description
w
w
w
A12
0
CAS Latency
010 2
011 3
Note: All other bit combinations are RESERVED.
Burst Type
0
1
Burst Length
001 2
010 4
011 8
100 16
Note: All other bit combinations are RESERVED.
A11
0
Sequential
Interleaved
A10
0
A9
0
A8
0
(BA[1:0] = 00
A7
7
0
B
A6
)
CL
A5
A4
512-Mbit DDR Mobile-RAM
HY[B/E]18M512160BF
BT
A3
Functional Description
07092007-3E44-UTNM
A2
Rev.1.80, 2006-11
BL
A1
A0