HYB18M512160BF-7.5 QIMONDA [Qimonda AG], HYB18M512160BF-7.5 Datasheet - Page 15

• Manufacturer Part Number: HYB18M512160BF-7.5
• Description: DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM RoHS compliant
• Manufacturer: QIMONDA [Qimonda AG]

Table 11
Parameter
Auto precharge write recovery + precharge time
Internal write to Read command delay
Self refresh exit to next valid command delay
Exit power down delay
CKE minimum high or low time
Refresh period
Average periodic refresh interval (8192 rows)
1) 0 C
2) All parameters assume proper device initialization.
3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference
4) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
5) The output timing reference level is V
6) Parameters
7) Min (t
8) t
9) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
10) DQ, DM and DQS input slew rate is measured between
11) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
12) Input slew rate
13) Input slew rate
14) These parameters guarantee device timing. They are verified by device characterization but are not subject to production
15) The transition time for address and command inputs is measured between
16) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
17) t
18) t
19) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
20) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
Internet Data Sheet
level for signals other than CK/CK is V
intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented
by a production tester. For half drive strength with a nominal load of 10pF parameters t
the same range. However, these parameters are not subject to production test but are estimated by device
characterization. Use of IBIS or other simulation tools for system validation is suggested.
this value can be greater than the minimum specification limits for t
t
one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin
skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
transitions through the DC region must be monotonic.
test.
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
any given cycle.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t
system performance (bus turnaround) will degrade accordingly.
QH
CH
HZ
DQSQ
). t
and t
= t
CL
QHS
consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for
HP
T
, t
C
LZ
- t
CH
accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on
AC Characteristics
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
QHS
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
70 C (comm.); -25 C
t
ac
, where t
and
1.0 V/ns..
0.5V/ns and < 1.0 V/ns.
t
DQSCK
HP
= minimum half clock period for any given cycle and is defined by clock high or clock low (t
are specified for full drive strength and a reference load as shown below. This circuit is not
1)2)3)4)
T
DDQ
C
DDQ
(cont’d)
/2.
85 C (ext.);
/2.
V
DD
V
15
ILD(DC)
=
Symbol
V
t
t
t
t
t
t
WTR
t
REFI
XSR
CKE
REF
DDQ
DAL
XP
and
CL
=
V
1.70 V - 1.90 V. All voltages referenced to
and t
IHD(AC)
t
CK
min.
120
(t
1
2
–
–
+t
(t
WR
CH
V
IS
RP
(rising) or
IH
).
- 6
/t
/t
CK
and
CK
max.
) +
7.8
)
64
–
–
–
–
512-Mbit DDR Mobile-RAM
V
IL
AC
.
V
IHD(DC)
and
t
HY[B/E]18M512160BF
CK
min.
120
DQSS
Electrical Characteristics
1
2
–
–
+t
t
DQSCK
IS
and
- 7.5
.
07092007-3E44-UTNM
max.
V
are expected to be in
7.8
64
ILD(AC)
Rev.1.80, 2006-11
–
–
–
–
(falling).
Unit Notes
ms –
t
t
t
ns
ns
µs
CK
CK
CK
V
23)
–
22)
–
24)
SS
.
CL
,