HYB18M512160BF-7.5 QIMONDA [Qimonda AG], HYB18M512160BF-7.5 Datasheet
HYB18M512160BF-7.5
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HYB18M512160BF-7.5 Summary of contents
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... HYB18M512160BF-6; HYE18M512160BF-6 HYE18M512160BF-7.5 Revision History: Rev.1.80 Previous Version: 1.70 all converted into QAG template 18 table 15: added typ. values We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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... CKmax t Access Time ( ) ACmax Table 2 Memory Addressing Scheme Item Banks Rows Columns 1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers ...
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... Table 3 Ordering Information 1) Type Package Commercial Temperature Range HYB18M512160BF-6 P-VFBGA-60-1 HYB18M512160BF-7.5 P-VFBGA-60-1 Extended Temperature Range HYE18M512160BF-6 P-VFBGA-60-1 HYE18M512160BF-7.5 P-VFBGA-60-1 1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range) 18M: 1.8V DDR Mobile-RAM 512: 512 MBit density 160: 16 bit interface width ...
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... Description The HY[B/E]18M512160BF is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a quad-bank DRAM. The HY[B/E]18M512160BF uses a double-data-rate architecture to achieve high-speed operation. The double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one- half clock cycle data transfers at the I/O pins ...
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... Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH) ...
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... Functional Description The 512-Mbit DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command ...
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Function Truth Tables Table 5 Truth Table - CKE CKEn-1 CKEn Current State L L Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks ...
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Table 6 Current State Bank n - Command to Bank n Current State CS RAS CAS WE Command / Action Any Idle Row Active L ...
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All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with ...
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Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not ...
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Electrical Characteristics 3.1 Operating Conditions Table 8 Absolute Maximum Ratings Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those ...
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Table 10 Electrical Characteristics Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Address and Command Inputs (BA0, BA1 A12, CKE, CS, RAS, CAS, WE) Input high voltage Input low ...
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AC Characteristics 1)2)3)4) Table 11 AC Characteristics Parameter DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time DQ and DM input setup time DQ ...
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Table 11 AC Characteristics Parameter Auto precharge write recovery + precharge time Internal write to Read command delay Self refresh exit to next valid command delay Exit power down delay CKE minimum high or low time Refresh period Average ...
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A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system recommended to turn off the weak pull-down element during read and write bursts (DQS ...
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Operating Currents Table 14 Maximum Operating Currents Parameter & Test Conditions Operating one bank active-precharge current CKE is HIGH HIGH between valid commands; address inputs RC RCmin CK CKmin ...
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Input slew rate is 1.0 V/ns. 4) Definitions for IDD: LOW is defined DDQ HIGH is defined DDQ STABLE is defined as inputs stable at a HIGH ...
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Pullup and Pulldown Characteristics Table 16 Full Drive Strength and Half Drive Strength Full Drive Strength PD Current (mA) Voltage (V) min. max. 0.00 0.00 0.00 0.10 2.80 18.53 0.20 5.60 26.80 0.30 8.40 32.80 0.40 11.20 37.05 0.50 ...
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Package Outlines Figure 5 P-VFBGA-60-1 (Plastic Very Thin Fine Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Qimonda Internet Page “Products”: http://www.qimonda.com/products. SMD = Surface Mounted Device Internet Data ...
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... List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 2 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 3 Ordering Information Table 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 5 Truth Table - CKE Table 6 Current State Bank n - Command to Bank Table 7 Current State Bank n - Command to Bank m (different bank Table 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 9 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 10 Electrical Characteristics ...
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List of Figures Figure 1 Standard Ballout 512-Mbit DDR Mobile-RAM (Top View ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2006-11 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...