HYB18M512160BF-7.5 QIMONDA [Qimonda AG], HYB18M512160BF-7.5 Datasheet - Page 17

• Manufacturer Part Number: HYB18M512160BF-7.5
• Description: DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM RoHS compliant
• Manufacturer: QIMONDA [Qimonda AG]

3.3
Table 14
Parameter & Test Conditions
Operating one bank active-precharge current:
t
are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current:
all banks idle, CKE is LOW; CS is HIGH, t
SWITCHING; data bus inputs are STABLE
Precharge power-down standby current with clock stop:
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current:
all banks idle, CKE is HIGH; CS is HIGH, t
SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current with clock stop:
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, t
SWITCHING; data bus inputs are STABLE
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, t
SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
Operating burst read current:
one bank active; BL = 4; CL = 3; t
I
Operating burst write current:
one bank active; BL = 4; t
address inputs are SWITCHING; 50% data change each burst transfer
Auto-Refresh current:
t
SWITCHING; data bus inputs are STABLE
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus
inputs are STABLE
Deep Power Down current
1) 0 C
2) IDD specifications are tested after the device is properly intialized and measured at 133 MHz for -7.5 and 166 MHz for -6
Internet Data Sheet
RC
OUT
RC
= t
= t
Recommended Operating Conditions unless otherwise noted
speed grade.
= 0 mA; address inputs are SWITCHING; 50% data change each burst transfer
RCmin
RFCmin
; t
; t
CK
T
CK
C
Operating Currents
Maximum Operating Currents
= t
= t
CKmin
CKmin
70 C (comm.); -25 C
; CKE is HIGH; CS is HIGH between valid commands; address inputs
; burst refresh; CKE is HIGH; address and control inputs are
CK
= t
CKmin
CK
; continuous write bursts;
= t
CKmin
CK
CK
; continuous read bursts;
= t
CK
= t
CK
T
C
CKmin
= t
CKmin
= t
1)2)3)4)5)
CKmin
CKmin
; address and control inputs are
85 C (ext.);
; address and control inputs are
; address and control inputs are
; address and control inputs are
17
V
DD
=
V
DDQ
=
1.70 V - 1.90 V.
512-Mbit DDR Mobile-RAM
Symbol
I
I
I
I
I
I
I
I
I
I
DD2NS
DD3NS
DD2PS
DD3PS
HY[B/E]18M512160BF
I
I
I
I
DD4W
DD2P
DD2N
DD3P
DD3N
DD4R
DD0
DD5
DD6
DD8
Electrical Characteristics
07092007-3E44-UTNM
see
0.70
0.60
105
110
185
1.5
1.5
2.5
- 6
70
18
25
Rev.1.80, 2006-11
2
Values
Table 15
25
6)
- 7.5
0.70
0.60
135
1.5
1.5
2.5
50
15
22
75
75
2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
A