W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 55

• Manufacturer Part Number: W9751G6KB
• Description: 8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
• Manufacturer: WINBOND [Winbond]

43. tIS and tIH (input setup and hold) derating.
Command/
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and
tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded „VREF(dc) to AC region‟, use nominal slew rate for derating value. See Figure 20 Illustration of nominal slew rate for tIS.
If the actual signal is later than the nominal slew rate line anywhere between shaded „VREF(dc) to AC region‟, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line
for tIS.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded „DC to VREF(dc) region‟, use nominal slew rate for derating value. See Figure 22 Illustration of nominal slew rate for tIH.
If the actual signal is earlier than the nominal slew rate line anywhere between shaded „DC to VREF(dc) region‟, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of
tangent line for tIH.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the
derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Slew Rate
Address
(V/nS)
0.25
0.15
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
tIS/tIH Derating values for DDR2-667, DDR2-800 and DDR2-1066
-1000
+150
+143
+133
+120
+100
ΔtIS
-100
-168
-200
-325
-517
+67
-13
-22
-34
-60
-5
0
2.0 V/nS
ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800 and DDR2-1066
-1125
ΔtIH
-125
-188
-292
-375
-500
-708
+94
+89
+83
+75
+45
+21
-14
-31
-54
-83
0
CLK/ CLK Differential Slew Rate
+180
+173
+163
+150
+130
ΔtIS
-138
-170
-295
-487
-970
+97
+30
+25
+17
-30
-70
+8
-4
- 55 -
1.5 V/nS
-1095
+124
+119
+113
+105
ΔtIH
-158
-262
-345
-470
-678
+75
+51
+30
+16
-24
-53
-95
-1
Publication Release Date: Dec. 09, 2011
+210
+203
+193
+180
+160
+127
ΔtIS
-108
-140
-265
-457
-940
+60
+55
+47
+38
+26
-40
0
1.0 V/nS
W9751G6KB
-1065
+154
+149
+143
+135
+105
ΔtIH
-128
-232
-315
-440
-648
+81
+60
+46
+29
-23
-65
+6
Revision A01
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