W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 41

no-image

W9751G6KB

Manufacturer Part Number
W9751G6KB
Description
8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
Manufacturer
WINBOND [Winbond]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W9751G6KB-18
Manufacturer:
WINBOND
Quantity:
7 600
Part Number:
W9751G6KB-18
Manufacturer:
Winbond
Quantity:
9 680
Company:
Part Number:
W9751G6KB-18
Quantity:
245
Company:
Part Number:
W9751G6KB-18
Quantity:
20 000
Part Number:
W9751G6KB-25
Manufacturer:
ISSI
Quantity:
3 140
Part Number:
W9751G6KB-25
Manufacturer:
Winbond Electronics
Quantity:
10 000
Part Number:
W9751G6KB-25
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
W9751G6KB-25
Quantity:
98
Company:
Part Number:
W9751G6KB-25
Quantity:
20
Company:
Part Number:
W9751G6KB-25
Quantity:
203
Notes:
1. V
2. I
3. Input slew rate is specified by AC Parametric Test Condition.
4. I
5. Data Bus consists of DQ, LDM, UDM, LDQS, LDQS , UDQS and UDQS .
6. Definitions for I
7. The following I
I
and the 2X refresh option is still enabled)
I
DD
DD
DD3P
I
DD4W
DD5B
DD
I
I
DD6
DD7
LOW = V
HIGH = V
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at V
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
specifications are tested after the device is properly initialized.
parameters are specified with ODT disabled.
= 1.8 V
(slow) must be derated by 30 % and I
in
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL
t
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Burst Refresh Current
t
Refresh command every t
CKE is HIGH, CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self Refresh Current
CKE
Other control and address inputs are FLOATING;
Data bus inputs are FLOATING. (T
Operating Bank Interleave Read Current
All bank interleaving reads, I
BL = 4, CL = CL
t
t
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
in
CK
CK
CK
RCD(IDD)
0.1V; V
DD
DD
= t
= t
= t
V
V
IL (ac) (max)
values must be derated (I
IH (ac) (min)
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
CK(IDD)
CK(IDD)
CK(IDD)
0.2 V, external clock off, CLK and CLK at 0 V;
;
DDQ
; t
;
, t
= 1.8 V
REF
RAS
RC
(IDD),
(IDD),
= t
= V
= t
RC(IDD)
AL = 0;
AL = t
DDQ
RASmax(IDD)
0.1V.
RFC(IDD)
/2
RCD(IDD)
OUT
, t
DD6
DD
RRD
= 0mA;
limits increase), when T
CASE
interval;
, t
must be derated by 80 %. (I
= t
RP
- 1 x t
RRD(IDD)
= t
85°C)
CK(IDD)
RP(IDD)
- 41 -
, t
RCD
;
;
=
CASE
200
105
245
6
DD6
Publication Release Date: Dec. 09, 2011
85°C I
will increase by this amount if T
165
200
95
6
DD2P
must be derated by 20 %;
150
180
90
6
W9751G6KB
mA
mA
mA
mA
Revision A01
CASE
1,2,3,4,5,
1,2,3,4,5,
1,2,3,4,5,
1,2,3,4,5,
6,7
6
6
6
< 85°C

Related parts for W9751G6KB