W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 28

• Manufacturer Part Number: W9751G6KB
• Description: 8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
• Manufacturer: WINBOND [Winbond]

This feature allows the precharge operation to be partially or completely hidden during burst read
cycles (dependent upon CAS Latency) thus improving system performance for random data access.
The RAS lockout circuit internally delays the Precharge operation until the array restore operation
has been completed (t
read or write command.
7.7.1
If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged.
The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles
later from the Read with AP command if t
waveform refer to 10.22 Burst read operation with Auto-precharge diagram in Chapter 10)
If t
t
If t
t
In case the internal precharge is pushed out by t
next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-
precharge to the next Activate command becomes AL + RU{ (t
waveform refer to 10.23 Burst read operation with Auto-precharge diagram in Chapter 10.), for BL = 8
the time from Read with Auto-precharge to the next Activate command is AL + 2 + RU{ (t
t
not start earlier than two clocks after the last 4-bit prefetch.
A new bank active command may be issued to the same bank if the following two conditions are
satisfied simultaneously.
(Example timing waveforms refer to 10.24 to 10.25 Burst read with Auto-precharge followed by an
activation to the same bank (t
7.7.2
If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged.
The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write
plus write recovery time (WR) programmed in the mode register. The bank undergoing Auto-
precharge from the completion of the write burst may be reactivated if the following two conditions are
satisfied.
(Example timing waveforms refer to 10.26 to 10.27 Burst write with Auto-precharge (t
(WR + t
RAS
RTP
CK(avg)
RAS
RTP




(min) is satisfied.
(min) is satisfied.
(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until
(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until
The RAS precharge time (t
begins.
The RAS cycle time (t
The data-in to bank activate delay time (WR + t
The RAS cycle time (t
RP
Burst read with Auto-precharge
}, where RU stands for “rounded up to the next integer”. In any event internal precharge does
Burst write with Auto-precharge
Limit) diagram in Chapter 10)
RAS
satisfied) so that the Auto-precharge command may be issued with any
RC
RC
RC
) from the previous bank activation has been satisfied.
) from the previous bank activation has been satisfied.
Limit) and (t
RP
) has been satisfied from the clock at which the Auto-precharge
RP
RAS
Limit) diagram in Chapter 10)
RTP
(min) and t
- 28 -
, t
RP
RP
) has been satisfied.
starts at the point where t
RTP
RTP
(min) are satisfied. (Example timing
Publication Release Date: Dec. 09, 2011
+ t
RP
) / t
CK(avg)
W9751G6KB
RTP
} (Example timing
ends (not at the
RC
Revision A01
RTP
Limit) and
+ t
RP
) /