HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 82

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
4.2
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked because of the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
Rev. 2.0, 03/02, page 58 of 298
When the address break is specified in instruction execution cycle
Operation
Register setting
• ABRKCR = H'80
• BAR = H'025A
Address
bus
Interrupt
request
Figure 4.2 Address Break Interrupt Operation Example (1)
prefetch
instruc-
NOP
0258
tion
prefetch
instruc-
NOP
Program
*
025A
tion
0258
025A
025C
0260
0262
:
Interrupt acceptance
prefetch
instruc-
tion 1
MOV
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
025C
:
prefetch
instruc-
tion 2
MOV
025E
processing
Internal
Underline indicates the address
to be stacked.
SP-2
Stack save
SP-4