HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 73

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

3.4.2
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a
SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.
3.4.3
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
When pins
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
Internal Interrupts
Interrupt Handling Sequence
ø
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
to
are designated for interrupt input in PMR5 and the designated
Figure 3.1 Reset Sequence
Vector fetch
Reset cleared
(2)
(1)
Internal
processing
Rev. 2.0, 03/02, page 49 of 298
Initial program
instruction prefetch
(2)
(3)