HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 142

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

10.4
10.4.1
1. According to table 10.2, six internal/external clock signals output by prescaler S can be
2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0
3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B
4. When a compare match A or B is generated, the TMOV responds with the output value
5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding
6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the
7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is
Rev. 2.0, 03/02, page 118 of 298
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 10.2 shows the count timing with an internal clock signal
selected, and figure 10.3 shows the count timing with both edges of an external clock signal
selected.
will be set. The timing at this time is shown in figure 10.4. An interrupt request is sent to the
CPU when OVIE in TCRV0 is 1.
(CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The
compare-match signal is generated in the last state in which the values match. Figure 10.5
shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in
TCRV0 is 1.
selected by bits OS3 to OS0 in TCSRV. Figure 10.6 shows the timing when the output is
toggled by compare match A.
compare match. Figure 10.7 shows the timing.
input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.
Figure 10.8 shows the timing.
halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by
TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
Internal clock
TCNTV input
clock
TCNTV
ø
Operation
Timer V Operation
Figure 10.2 Increment Timing with Internal Clock
N – 1
N
N + 1