HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 108

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HD64F3670

Manufacturer Part Number
HD64F3670
Description
Hitachi Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Rev. 2.0, 03/02, page 84 of 298
Note: *The RTS instruction must not be used during the following 1. and 2. periods.
Wait (Wait time=programming time)
Write pulse application subroutine
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Clear PSU bit in FLMCR1
Set PSU bit in FLMCR1
Clear P bit in FLMCR1
Set P bit in FLMCR1
Apply Write Pulse
WDT enable
Disable WDT
Wait 50 s
Wait 5 s
Wait 5 s
End Sub
Figure 7.3 Program/Program-Verify Flowchart
*
Increment address
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
No
Additional-programming data computation
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
Clear SWE bit in FLMCR1
Set block start address as
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
End of programming
Apply Write Pulse
Apply
Read verify data
verify address
Wait 100 s
Yes
Yes
Verify data =
write data?
Wait 1 s
Wait 4 s
Wait 2 s
Yes
Wait 2 s
128-byte
START
m= 0 ?
n 6 ?
m= 0
n 6?
n= 1
Write pulse
Yes
Yes
Sub-Routine-Call
No
No
No
No
*
m = 1
Clear SWE bit in FLMCR1
Programming failure
Wait 100 s
n
1000 ?
No
Yes
n
n + 1

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