HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 215

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

13.7
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 13.6
shows the interrupt sources.
Table 13.6 SCI3 Interrupt Requests
Interrupt Requests
Receive Data Full
Transmit Data Empty
Transmission End
Receive Error
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent
the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
13.8
13.8.1
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
13.8.2
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or
send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin
becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission,
first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
Interrupts
Usage Notes
Break Detection and Processing
Mark State and Break Sending
Abbreviation
RXI
TXI
TEI
ERI
Interrupt Sources
Setting RDRF in SSR
Setting TDRE in SSR
Setting TEND in SSR
Setting OER, FER, and PER in SSR
Rev. 2.0, 03/02, page 191 of 298