HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 314

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
7.2.4 Flash Memory
Enable Register (FENR)
7.3 On-Board
Programming Modes
Table 7.1 Setting
Programming Modes
7.3.1 Boot Mode
Table 7.2 Boot Mode
Operation
7.4.1 Program/Program-
Verify
Rev. 2.0, 03/02, page 290 of 298
Page
79
79
81
83
Revisions (See Manual for Details)
Description amended.
Bit 7 (FLSHE) in FENR enables or disables the CPU
access to the flash memory control registers,
FLMCR1, FLMCR2, and EBR1.
Description amended.
EIOT_0
Changed.
Description amended.
7.
For a dummy write to a verify address, write 1-
byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words or in
longwords from the address to which a dummy
write was performed.
Transmits data H'55 when data H'00
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
Continuously transmits data H'00
H'AA reception
H'AA reception
is received error-free.
at specified bit rate.
Processing Contents
Host Operation
E10T_0
Boot program
erase error
Communication Contents
Upper bytes, lower bytes
H'00, H'00 . . . H'00
Echoback
Echoback
H'XX
H'AA
H'00
H'55
H'FF
H'AA
Transmits data H'AA to host when data H'55
is received.
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
• Measures low-level period of receive data
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Branches to boot program at reset-start.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
H'00.
end indication.
Boot program initiation
Processing Contents
LSI Operation
Rev.
2.0
2.0
2.0
2.0