MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 83
MC68HC908JK3EMP
Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3EMP.pdf
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7.4.2 Active Resets from Internal Sources
MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
All internal reset sources actively pull the RST pin low for 32 2OSCOUT
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles
An internal reset can be caused by an illegal address, illegal opcode,
COP time-out, or POR. (See
Note that for POR resets, the SIM cycles through 4096 2OSCOUT
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
2OSCOUT
—
IRST
RST
IAB
Rev. 2.0
7-5.
System Integration Module (SIM)
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
Figure 7-6. Sources of Internal Reset
Figure 7-5. Internal Reset Timing
RST PULLED LOW BY MCU
COPRST
32 CYCLES
POR
Figure 7-6 . Sources of Internal
LVI
INTERNAL RESET
System Integration Module (SIM)
32 CYCLES
Reset and System Initialization
(Figure
VECTOR HIGH
Technical Data
Reset.)
7-5).
83
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