MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 99
MC68HC908JK3EMP
Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3EMP.pdf
(226 pages)
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MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
Address:
POR — Power-On Reset Bit
PIN — External Reset Bit
COP — Computer Operating Properly Reset Bit
ILOP — Illegal Opcode Reset Bit
ILAD — Illegal Address Reset Bit (opcode fetches only)
MODRST — Monitor Mode Entry Module Reset bit
LVI — Low Voltage Inhibit Reset bit
Read:
Write:
POR:
—
1 = Last reset caused by POR circuit
0 = Read of SRSR
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
1 = Last reset caused by COP counter
0 = POR or read of SRSR
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
1 = Last reset caused by monitor mode entry when vector locations
0 = POR or read of SRSR
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
Rev. 2.0
$FE01
POR
Bit 7
$FFFE and $FFFF are $FF after POR while IRQ1 = V
1
System Integration Module (SIM)
Figure 7-21. Reset Status Register (RSR)
= Unimplemented
PIN
6
0
COP
5
0
ILOP
4
0
ILAD
3
0
System Integration Module (SIM)
MODRST
2
0
LVI
1
0
Technical Data
SIM Registers
DD
Bit 0
0
0
99
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