MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 55

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
NOTE:
Address:
COPRS — COP reset period selection bit
LVID — Low Voltage Inhibit Disable Bit
SSREC — Short Stop Recovery Bit
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP — STOP Instruction Enable
COPD — COP Disable Bit
Reset:
Read:
Write:
SSREC enables the CPU to exit stop mode with a delay of
32 × 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay.
STOP enables the STOP instruction.
COPD disables the COP module. (See
Operating Properly
—
1 = COP reset cycle is (2
0 = COP reset cycle is (2
1 = Low Voltage Inhibit disabled
0 = Low Voltage Inhibit enabled
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Rev. 2.0
COPRS
$001F
Bit 7
Figure 5-2. Configuration Register 1 (CONFIG1)
R
0
Configuration Register (CONFIG)
= Reserved
R
6
0
(COP).)
R
5
0
13
18
LVID
– 2
– 2
4
0
4
4
) × 2OSCOUT
) × 2OSCOUT
R
Section 15. Computer
3
0
Configuration Register (CONFIG)
SSREC
2
0
Functional Description
STOP
1
0
Technical Data
COPD
Bit 0
0
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