PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 86

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PEB20534H-10

Manufacturer Part Number
PEB20534H-10
Description
DMA Supported Serial Communication Controller with 4 Channels DSCC4
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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Semiconductor Group
Table 16
Offset
Addr.
0048
H
Access
Type
Bit-Fields
Pos.
31..27,
26..22,
21..17,
15..11
7,5,3,1
6,4,2,0
r/w
Central FIFO Control Registers (cont’d)
Controlled
by
CPU
Name
TFR
THRESH0,
TFR
THRESH1,
TFR
THRESH2,
TFR
THRESH3,
M4_i
M2_i
Reset
Value
00000000
Default
0,
0,
0,
0
0
0
86
H
Register Name
FIFOCR2:
FIFO Control Register 2
Description
Transmit FIFO Refill Threshold i (i=0..3)
Transmit FIFO Refill Threshold for the
corresponding channel i in number of
DWORDs multiplied by its respective
multiplier Mx_i.
This threshold controls DMAC operation
towards the Host memory. A watermark
is calculated by:
watermark = TFRTHRESHi*Mx_i+1.
As soon as the number of valid data in
the transmit FIFO section is less than the
watermark, the DMA controller requests
for new data from shared memory.
Multiplier 4
Multiplier 2
DMA Controller and Central FIFOs
Data Sheet 09.98
PEB 20534

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