PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 74

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
In ASYNC mode and BISYNC mode to every data byte an attached status byte can be
stored. This byte is forwarded transparently from the SCC to the data buffer and it
contains status information such as: parity, parity error, framing error.
Since the threshold of the SCC specific receive FIFOs can be set to 1, 2, 4, 16 or
24 bytes the receive data buffer DWORDs can contain less than four valid bytes (e.g. 1
or 2 bytes) In this case the data buffer contains holes of invalid data bytes. Refer to
Table 69, “CCR2: Channel Configuration Register 2,” on page 296.
Table 15 provides examples for the receive data section.
Table 15
Mode
HDLC (Default) 4
HDLC
(Default)
ASYNC
(RFDF=1
RFTH=00)
Note: In general, BNO counts the valid bytes that have been transferred into the data
buffer including RSTA (BNO <= NO). The receive status byte (RSTA) is treated
and counted as ’data’ by the DMA controller. As an example, an HDLC frame
containing 32 bytes to be transferred to the shared memory needs 33 bytes in the
receive data buffer due to the receive status byte, which is attached to the data by
the SCC. If NO =32 in this example, the receive status byte as well as the frame
end indication will be written to the next data buffer and descriptor respectively.
Receive Data Buffer Section
BNO Little Endian
7
6
11
RSTA byte 2 byte 1
byte 3 byte 2 byte 1
10
RSTA byte 5
01
status 0 data 0 data 0 status 0
status 1 data 1 data 1 status 1
status 2 data 2 data 2 status 2
74
byte 0 byte 0 byte 1
00
byte 0 byte 0 byte 1
byte 4 byte 4 byte 5
DMA Controller and Central FIFOs
Big Endian
11
10
Data Sheet 09.98
01
byte 2 RSTA
byte 2 byte 3
RSTA
PEB 20534
00