PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 252

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Table 50
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit 31
Bit 15
IQSCCi
TXBAR
30
14
IQSCCiTXBAR:
Interrupt Queue SCCi Receiver Base Address Register (i=0...3)
i = 3...0
These registers determine the base address of the respective transmit
interrupt queue and can be located anywhere in the 32 bit address
range.
Note: The interrupt queue base addresses must be 32-bit aligned, i.e. bit
29
13
28
12
1 and 0 must be set to ’0’.
read/write
0000 000
Channel 0
0024
written by CPU
evaluated by DSCC4
27
11
H
IQSCCiTXBAR(15:2)
H
26
10
IQSCCiTXBAR(31:16)
Channel 1
0028
25
9
H
24
8
252
23
7
Channel 2
002C
22
6
Detailed Register Description
H
21
5
20
4
Channel 3
0030
19
(TX Channel 3...0)
3
H
Data Sheet 09.98
18
2
PEB 20534
17
1
0
16
0
0