PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 78

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
5.1.2.4
This mode is selected by setting bit CMODE=’1’ in register GMODE (See “GMODE:
Global Mode Register” on page 241.).
The DMA controller operates on linked lists with pointer information stored in the DSCC4
internal configuration section.
The initialization procedure as well as the CPU to DSCC4 handshaking is equal to the
HOLD-Bit control mode as described in Chapter 5.1.2.3 with the following exception:
The host CPU does not take care about the HOLD bit. The address of the descriptor in
the chain at which a ’Hold’ is to be exercised is written to the corresponding LTDA/LRDA
register. The DMA channel compares its current (first) descriptor address to
LTDA/LRDA. When a match occures, a ’Hold’ condition is activated. After attaching at
least one new descriptor to the linked list. Also the DMA channel does not take care on
the HOLD bit within the descriptors but compares its current descriptor address with
LTDA/LRDA register value. In case of address match this condition is equal to the
HOLD-condition.
Figure 17
After initialization the DMAC internally starts with the Base Tx/Rx Descriptor Address
BTDA/BRDA as the “first descriptor address“ since this address points to the first
DSCC4 Register
*) FTDA starts with BTDA and is updated by the DSCC4 until FTDA=LTDA
**) FRDA starts with BRDA and is updated by the DSCC4 until FRDA=LRDA
CHiFRDA**)
CHiFTDA*)
CHiBRDA
CHiBTDA
CHiLRDA
CHiLTDA
DMAC Operation Using Last Descriptor Address Control Mode
Data Transfer controlled via first and last descriptor addresses
Shared Memory
78
DMA Controller and Central FIFOs
Data Sheet 09.98
PEB 20534