PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 253

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 51
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Semiconductor Group
Bit 31
Bit 15
IQCFGBAR
30
14
IQCFGBAR:
Interrupt Queue Configuration Base Address Register
This register determins the base address of the configuration interrupt
queue and can be located anywhere in the 32 bit address range.
Note: The interrupt queue base address must be 32-bit aligned, i.e. bit 1
29
13
28
12
and 0 must be set to ’0’.
read/write
0000 000
003C
written by CPU
evaluated by DSCC4
27
11
H
H
26
10
IQCFGBAR(15:2)
25
IQCFGBAR(31:16)
9
24
8
253
23
7
22
6
Detailed Register Description
21
5
20
4
19
3
Data Sheet 09.98
18
2
PEB 20534
17
1
0
16
0
0
(-)