PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 84
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PEB20534H-10
Manufacturer Part Number
PEB20534H-10
Description
DMA Supported Serial Communication Controller with 4 Channels DSCC4
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.PEB20534H-10.pdf
(442 pages)
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• Interrupt queue polling:
The two solutions can be mixed. Queues with high interrupt activity might be serviced by
periodic queue polling and other queues on INTA and GSTAR indication only. In this
case the ISR only takes care on some GSTAR bits but must confirm all indications to
reset INTA indication.
Note that any interrupt event will cause an INTA and GSTAR indication.
To distinguish between old and new interrupt vectors in the circular queues, vectors can
be overwritten by software with all zeros. Because the number of new vectors is not
known, a queue read pointer can be incremented as long as no new vector is found at
this location.
queue specific bit positions in register GSTAR and all new vectors are read from the
corresponding interrupt queues afterwards. It is possible to confirm all indications by
one register access writing the value 0xFFFFFFFF
The interrupt queues are polled periodically for new vectors. Neither INTA signal nor
register GSTAR is evaluated.
84
DMA Controller and Central FIFOs
H
to GSTAR.
Data Sheet 09.98
PEB 20534
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