DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 69

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 60.
Default values are shown highlighted.
Table 61.
Default values are shown highlighted.
DAC1617D1G0 3
Preliminary data sheet
Bit
2
1
0
Bit
7
6
5 to 4
3 to 2
1 to 0
Symbol
LDAB_SWAP
IQ_FORMAT
EDGE_LDCLK
Symbol
SR_CDI
RESERVED
I_LEV_CNTRL[1:0]
Q_LEV_CNTRL[1:0]
CDI_MODE[1:0]
Register LD_CNTRL (address 0Ah)
Register MISC_CNTRL (address 0Bh)
Access
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
…continued
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Value
0
1
0
1
0
1
Value
0
1
0
00
01
10
11
00
01
10
11
00
01
10
11
Description
swaps LVDS A and LVDS B paths
specify IQ supplied format
specify sampling edge for LVDS data path
Description
CDI block software reset control
reserved
specifies output from CDI for I path
specifies output from CDI for Q path
specifies CDI mode
normal operation
LVDS A and LVDS B paths are swapped
folded
interleaved
falling edge of LDCLK
rising edge of LDCLK
no action
perform a software reset on CDI
normal operation (CDI data output sent to digital
signal processing input)
if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = I_DC_LEVEL register value
digital signal processing input = I_DC_LEVEL
digital signal processing input = I_DC_LEVEL
normal operation (CDI data output sent to digital
signal processing input)
if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = Q_DC_LEVEL register value
digital signal processing input = Q_DC_LEVEL
digital signal processing input = Q_DC_LEVEL
cdi_mode 0 (2 mode)
cdi_mode 1 (4 mode)
cdi_mode 2 (8 mode)
not used
DAC1617D1G0
© IDT 2012. All rights reserved.
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