DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 35

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.13.1.2 MDS in Master/slaves mode
10.13.2 MDS flexibility and constraints
In this mode, one DAC1617D1G0 device is used as master, the other one is used as
slave. The FPGA(s) still has(have) to provide the ALIGN signal to the DAC devices to
identify the LVDS data flow start (see Figure 23). The master generates the reference
MDS signal. The slave uses this signal to do the synchronization of the output. This mode
is recommended when only two DAC1617D1G0 devices must be synchronized.
Figure 25 shows the MDS Master/slaves mode schematic.
Getting a 1 clock period alignment can become very difficult without the MDS feature.
There are many sources of misalignment:
The DAC1617D1G0 MDS feature compensates these delays when:
Fig 26. MDS Master/slaves mode
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At 1 GHz, two signals with only 15 cm PCB length difference have a 1 clock period
skew. So the PCB traces off the FPGA reference clock, the LVDS data/clock, or the
DAC clock introduce delay.
The clock generation circuit can cause delay between the different clocks.
The most important delay comes from the internal FPGA design that can cause 1 or 2
LVDS clock delays between the different LVDS data patterns.
The overall delay compensated by the DAC1617D1G0 remains below 64 DAC clock.
Each FPGA has to activate its ALIGN signal with the beginning of the LVDS data flow
start (even if the different ALIGN signals are mis-aligned)
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
DAC1617D1G0
© IDT 2012. All rights reserved.
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