DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 65

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Table 53.
Address
0
1
2
4
5
6
8
9
10 0Ah
11
12 0Ch
13 0Dh
14 0Eh
15 0Fh
16 10h
00h
01h
02h
04h
05h
06h
08h
09h
0Bh
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Page_0A register allocation map
Register name
MAIN_CNTRL
MAN_LDCLKDEL
DBG_LVDS
RST_EXT_LDCLK
RST_EXT_DCLK
DCMSU_PREDIV
LD_POL_LSB
LD_POL_MSB
LD_CNTRL
MISC_CNTRL
I_DC_LVL_LSB
I_DC_LVL_MSB
Q_DC_LVL_LSB
Q_DC_LVL_MSB
IO_MUX0
10.22.7 Page A register allocation map
Table 53 shows an overview of all registers on page A (0Ah in hexadecimal).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PARITYC DESCRAMBLE
SR_CDI
Bit 7
-
-
-
RESERVED
Bit 6
-
-
-
Bit 5
-
-
-
SEL_EN[1:0]
CNTRL[1:0]
I_LEV_
RST_EXT_DCLK_TIME[7:0]
RST_EXT_LCLK_TIME[7:0]
DCMSU_PREDIVIDER[7:0]
LD_PD
Bit 4
Q_DC_LEVEL[15:8]
I_DC_LEVEL[15:8]
Q_DC_LEVEL[7:0]
IO_SELECT0[7:0]
I_DC_LEVEL[7:0]
-
-
LD_POL[15:8]
Bit definition
LD_POL[7:0]
WORD_SWAP
PD_CNTRL
SBER
Q_LEV_CNTRL[1:0]
Bit 3
LDCLK_DEL[3:0]
CNTRL
LDAB_
SWAP
CAL_
Bit 2
RESERVED
FORMAT
RST_
DCKL
Bit 1
CDI_MODE[1:0]
IQ_
EDGE_
LDCLK
RST_
LCKL
Bit 0
Default
Bin
0000
0011
0000
0000
0000
0000
0011
1111
0010
0000
0001
1101
0000
0000
0000
0000
0000
0011
0000
0000
0000
0000
1000
0000
0000
0000
1000
0000
1111
1111
Hex
03h
00h
00h
3Fh
20h
1Dh
00h
00h
03h
00h
00h
80h
00h
80h
FFh