DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 19

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
Fig 9.
A0
LVDS DDR data formats
B0
10.4.4 Input port formatting
A1
B1
A2
The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block
demultiplexes these two streams.
The two streams can carry two data formats:
The data format block is in charge of the data format adaptation (see Figure 9).
The DAC1617D1G0 can correctly decode the input stream using bit IQ_FORMAT of
register LD_CNTRL (see Table 60), because it can determine which format is used on the
LVDS DDR bus.
Table 10 shows the format mapping between the LVDS input data and the data sent to the
two DAC channels depending on the data format selected.
Table 10.
B2
Data format
interleaved format (IQ_FORMAT = 1)
folded format (IQ_FORMAT = 0)
Fig 8.
•
•
A3
Folded
Interleaved
A0
B3
LVDS DDR receiver mapping LDAB SWAP = 1
B0
Folded and interleaved format mapping
LD[15..0]P/N
LCLKP/N
A1
RECEIVER
LVDS
B1
PB[15..0]
PA[15..0]
LCLK
A2
Rev. 03 — 2 July 2012
B2
A0
B0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
A3
B3
A1
B1
LD[15..0]P/N
LCLKP/N
A2
B2
RECEIVER
LVDS
A3
B3
Data bit mapping
In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0]
In[15..8] = An[15..8]; In[7..0] = Bn[15..8]
Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0]
PB[15..0]
PA[15..0]
LCLK
FORMAT
DATA
DAC1617D1G0
B0
A0
Q0
I0
to DAC A
to DAC B
B1
A1
to DAC A
to DAC B
Q1
I1
Q2
B2
A2
I2
© IDT 2012. All rights reserved.
001aan395
001aan394
Q3
I3
B3
A3
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